/*
 * @Author: LC 1774939529@qq.com
 * @Date: 2023-11-05 17:50:10
 * @LastEditors: lc
 * @LastEditTime: 2023-11-06 17:35:28
 * @FilePath: \display_d_tube\RTL\top.v
 * @Description:  
 * 
 * Copyright (c) 2023 by ${git_name_email}, All Rights Reserved. 
 */
//`include "./digital_tube.v"

module top (
    input  clk_50Mhz, rst_n,
    output OE_n, shift_clock_cp, storage_clock_8div_cp, data_s 
);
    reg [4:0] count = 5'b0;
    reg flag = 1'b1;

    /* 8计数器 */
    always @(posedge clk_50Mhz) begin
        if(rst_n == 1'b0)begin
            count <= 5'b0;
            flag <= 1'b1;
        end else begin
            if(count == 5'b11010) begin
                count <= 5'b0;
                flag <= 1'b1;
            end else begin
                count <= count + 1'b1;
                flag <= 1'b0;
            end
        end
    end

    digital_tube u_digital_tube(
    	.clk_50Mhz             (flag                  ),
        .rst_n                 (rst_n                 ),
        .OE_n                  (OE_n                  ),
        .shift_clock_cp        (shift_clock_cp        ),
        .storage_clock_8div_cp (storage_clock_8div_cp ),
        .data_s                (data_s                )
    );
    
endmodule

